Fabrication of semiconductor integrated circuits or integrated optical circuits very often requires a smooth, planar surface. The surface requiring planarization involves areas or layers of dielectric material on or in a surface of a semiconductor material or on a surface of a previously interleaved layer. The insulating layers should have a smooth surface topography, because rough surfaces cause fabrication problems. It is difficult to image and pattern layers applied to rough surfaces, and this difficulty increases as the number of layers increases because each additional patterned layer contributes additional roughening. The topography of such dielectric areas or layers may be highly uneven and require polishing of the surface so as to present a smooth, planar surface for the next processing step, such as formation of a conductor layer or pattern on this surface. The uneven surface topography may be due to areas of dielectric material which are higher than the remainder of the surface or because of an uneven topography of underlying material or other elements of the semiconductor device being fabricated.
For example, in VLSI fabrication technology, connecting metal lines are formed over a semiconductor substrate containing device circuitry and serve to electrically interconnect the discrete devices. These connecting metal lines are typically insulated from the next interconnection level by thin layers of insulating material. In order to interconnect metal lines of different interconnection levels, holes are formed in the insulating layers to provide electrical access therebetween.
A recent development in the art is the use of lapping machines, and other planarization processes to provide smooth insulator topographics for the next metal level. In these processes it is often important to determine an end point of the polishing process, for example to remove a sufficient amount of material so as to provide a smooth, planar surface without removing underlying material. Thus, a precise endpoint detection technique is needed.
Presently, there are various types of lapping machines for reducing the thickness of semiconductor wafers. In general, these lapping machines include top and bottom plates (e.g. a polishing table and a wafer carrier or holder), between which the wafers are positioned. The plates are moved relative to each other, and a polishing slurry is fed between the semiconductor wafer and one plate to polish and flush away the wafer particles. An example of one such a lapping machine is disclosed in U.S. Pat. No. 3,063,206.
Traditionally, lasers and other optical detection devices have been employed to determine etch endpoints. However, such optical systems are difficult to implement in lapping machines, because in such machines the wafers are polished face down against a moving (e.g. spinning) polishing table. More particularly, the wafer is hidden under the top plate thereby making optical endpoint detection difficult.
A typical method employed for determining endpoint in lapping machines is to measure the amount of time needed to planarize the first wafer, and then to run the remaining wafers for similar times. In practice this method is extremely time consuming, since operators must inspect each wafer after polish. This is because it is extremely difficult to precisely control the rate of dielectric film removal for different wafers since the rate of removal may vary during the polishing of an individual wafer or because the rate of removal may diminish in the process of polishing a number of wafers in sequence.
Thus, a continuing need exists in the semiconductor devices fabrication art for a method and an apparatus which would accurately and efficiently detect the endpoint of a lapping planarization process.